This project, a collaboration with R. I. Bahar, W. R. Patterson, and Joe Mundy of Brown, focused on fundamental noise sources in ultimate CMOS (thermal, noise, random dopant fluctuations, radiation) and their effect on reliability. At the ultimate transistor dimensions and scaled supply voltages below 0.5 V, the number of electrons on any node in a digital circuit could drop to ~100-200, leading to reliability issues. We investigated time-to-failure modeling, as well as the possible logic design styles that could provide additional noise immunity, and time-domain thermal and RDF noise-driven fluctuations.

Funding agencies:
NSF CCF-0506732
DTRA HDTRA1-10-1-0013
NSF CCF-1525486

Key students and post-docs:
Pooya Jannaty (Brown PhD EE 2012)
Marco Donato (Brown PhD EE 2018 from Iris Bahar’s group, post-doc 2019, collaborator on the current cryo-CMOS and magnetic sensing project)
Elahe Rezaei (Brown post-doc EE 2021)